1. Field of the Invention
This invention relates to a noise reduction circuit in a signal processing channel, primarily for use in conjunction with a focal plane array (FPA) and, more specifically, to a noise reduction system for minimizing 1/f and other low frequency noise as well as errors caused by ambient low frequency magnetic fields. This invention also corrects for DC non-uniformities in the input signals (i.e., photodetectors).
2. Brief Description of the Prior Art
In accordance with the prior art focal plane array (FPA) detector systems, there is generally provided a plurality of photodetectors in an array, the output of each of the photodetectors being fed to an associated amplifier, the amplified output thereof being passed to a multiplexing circuit. The outputs, which are fed to the multiplexing circuit of the system, are serially read out to a post amplifier and are then fed to a bond pad on the single chip containing the entire circuit.
Certain scanning focal plane arrays have been found to encounter a significant low frequency magnetic field. This low frequency magnetic field causes considerable low frequency electrical voltages to be generated in the CMOS circuits and detectors which can be of sufficient magnitude to dwarf the relatively high frequency signal coming from the detectors of the FPA. Also, the CMOS circuitry and detectors produce significant low frequency 1/f noise which also degrades the signal to noise ratio. Little, if any, consideration was given to these low frequency noise components in the prior art systems of the above described type.